Improving the efficiency of AI accelerators and image processing in College of Engineering

According to the Public Relations Department of College of Engineering, researchers at the School of Electrical and Computer Engineering at the University of Tehran have designed an approximate floating-point multiplier called AFMIS (Approximate Floating-point Multiplier based on Input Segmentation) in a new study. This method uses input segmentation to significantly reduce energy consumption and hardware complexity while maintaining calculation accuracy in fault-tolerant applications.

This research was conducted by Asma NaseriRad, Dr. Shaghayegh Vahdat, and Dr. Ali Afzali-kusha, professors of the School of Electrical and Computer Engineering at the University of Tehran, in collaboration with Dr. Massoud Pedram from the University of Southern California, USA, and its results have been published in the prestigious journal Future Generation Computer Systems.

In this study, the researchers succeeded in eliminating the need for some complex and expensive hardware circuits by dividing the mantissa of floating-point numbers into several parts and performing multiplication operations only on the most significant non-zero parts. In addition to increasing processing speed, this method allows the level of accuracy of calculations to be adjusted according to the type of application.

The results of hardware evaluations show that the proposed architecture has been able to reduce latency by 81.7%, circuit area by 98%, and power consumption by 99% compared to precise floating-point multipliers. The optimized version of this architecture (E-AFMIS) also has significant improvements in energy consumption and hardware efficiency indicators.

To investigate the performance of this architecture in practical applications, the researchers evaluated it in JPEG image compression and deep learning models. The results showed that using the proposed multiplier had a very small impact on the accuracy of the output of these systems and in many cases, its performance was almost the same as that of exact multipliers.

In experiments conducted on deep neural networks including ResNet-18, VGG-16 and DenseNet-161, the proposed architecture has been able to significantly reduce energy consumption while maintaining data classification accuracy. Also, images compressed using this multiplier did not differ significantly in terms of visual quality from images produced by accurate methods.

This research achievement can pave the way for the development of a new generation of low-power and high-speed processors for applications such as artificial intelligence, machine learning, Internet of Things and image processing systems and play an effective role in improving the efficiency of future computing hardware.

This article can be viewed at the following link:

https://www.sciencedirect.com/science/article/abs/pii/S0167739X26000117